mirror of
https://github.com/libretro/dolphin
synced 2024-09-19 12:05:10 -04:00
6e61c32495
dspspy: remove some alignment for some vars. (should not have caused issues anyways) dspCodeUtil: pad ucodes converted to headers to 32byte multiples with nops (this is only mimicing what is seen in nintendo ucodes, probably because their's are originating on disc) Common.h: fix typo for gcc version of GC_ALIGNED32 (wtf? how did this work before?!) createtest.pl: add "jmp end_of_test" to the end of generated ucodes. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3994 8ced0084-cf51-0410-be5f-012b33b47a6e
187 lines
4.3 KiB
Plaintext
187 lines
4.3 KiB
Plaintext
; This ucode can copy the dsp instruction rom and coefficient table.
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; irom:
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; 0x8000 in instruction space
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; coef:
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; 0x1000 in data space
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;
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; Both irom and coef are 0x1000 words in length - remember, DSP
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; uses 16bit words
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;
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; The DSP has two address spaces, to load data from instruction
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; space you need to use 'i'-prefixed instructions.
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/********************************/
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/** HANDY THANGERS **/
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/********************************/
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; External
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MEM_BASE: equ 0x0000
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MEM_HI: equ MEM_BASE
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MEM_LO: equ MEM_BASE+1
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; DSP
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DRAM_BASE: equ 0x0000
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; Config reg controls dma behavior
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CR_TO_DSP: equ 0
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CR_TO_CPU: equ 1
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CR_IRAM: equ 2
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CR_DRAM: equ 0
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IROM_BASE: equ 0x8000
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COEF_BASE: equ 0x1000
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DUMP_SIZE: equ 0x2000 ; in bytes!
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/**************************************************************/
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/* CODE START */
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/**************************************************************/
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; iram 0x00 - Exception vectors
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; 8 vectors, 2 opcodes each
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jmp exception0
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jmp exception1
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jmp exception2
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jmp exception3
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jmp exception4
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jmp exception5
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jmp exception6
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jmp exception7
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; iram 0x10 - Our entry point
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sbset #0x02
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sbset #0x03
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sbclr #0x04
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sbset #0x05
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sbset #0x06
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; ???
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s16
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lri $CR, #0x00ff
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/**************************************************************/
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/* MAIN */
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/**************************************************************/
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; This ucode is meant only to dump the ROMs, and as such is
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; self-contained and skimpy
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main:
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clr $acc1
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clr $acc0
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; This consumes ALL of dram! We must be careful until we dma it!
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call copy_irom_to_dram
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; Send mail saying irom dump is done
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBL, #0xc0de
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si @DIRQ, #0x0001
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; Get address to dma to, dma, and wait till done
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call dma_dram_to_cmbl
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; Now we can start over for the coef
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call copy_coef_to_dram
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; Send mail saying coef dump is done
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBL, #0xda7a
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si @DIRQ, #0x0001
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; Get address to dma to, dma, and wait till done
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call dma_dram_to_cmbl
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; Die
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do_halt:
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halt
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/**************************************************************/
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/* HELPER FUNCTIONS */
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/**************************************************************/
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/********************************/
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/** DUMPING FUNCTIONS **/
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/********************************/
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; Dump irom from 0x8000 in instruction space
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copy_irom_to_dram:
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lri $ar0, #IROM_BASE
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lri $ar1, #DRAM_BASE
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lri $ar2, #DUMP_SIZE/2 ; each iteration copies a word
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bloop $ar2, copy_irom_to_dram_end
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ilrri $ac0.m, @$ar0
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; Now ac0.m is 16bits of irom!
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srri @$ar1, $ac0.m
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copy_irom_to_dram_end:
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nop
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ret
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; Dump coef from 0x1000 in data space
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copy_coef_to_dram:
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lri $ar0, #COEF_BASE
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lri $ar1, #DRAM_BASE
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lri $ar2, #DUMP_SIZE/2 ; each iteration copies a word
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bloop $ar2, copy_coef_to_dram_end
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lrri $ac0.m, @$ar0
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; Now ac0.m is 16bits of coef!
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srri @$ar1, $ac0.m
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copy_coef_to_dram_end:
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nop
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ret
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/********************************/
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/** DMA **/
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/********************************/
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; DMA implementation which does not write to dram
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; We take advantage of the fact that we know the mail is going to
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; contain the address which we should dma to
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dma_dram_to_cmbl:
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call wait_for_cpu_mbox
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lrs $ac0.m, @CMBL
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andi $ac1.m, #0x7fff
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; Directly do dma; writing the length kicks it off
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sr @DSMAH, $ac1.m
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sr @DSMAL, $ac0.m
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si @DSPA, #DRAM_BASE
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si @DSCR, #(CR_TO_CPU|CR_DRAM)
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si @DSBL, #DUMP_SIZE
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; Waits for previous DMA to complete by watching a bit in DSCR.
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wait_dma:
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lrs $ac1.m, @DSCR
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andcf $ac1.m, #0x0004
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jlz wait_dma
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ret
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/********************************/
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/** MAILBOX **/
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/********************************/
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; Waits for a mail to arrive in the DSP in-mailbox.
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wait_for_dsp_mbox:
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lrs $ac1.m, @DMBH
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andcf $ac1.m, #0x8000
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jlz wait_for_dsp_mbox
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ret
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; Waits for the CPU to grab a mail that we just sent from the DSP.
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wait_for_cpu_mbox:
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lrs $ac1.m, @CMBH
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andcf $ac1.m, #0x8000
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jlnz wait_for_cpu_mbox
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ret
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/********************************/
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/** EXCEPTION HANDLERS **/
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/********************************/
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; ...zey do nutzing!
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exception0:
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rti
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exception1:
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rti
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exception2:
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rti
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exception3:
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rti
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exception4:
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rti
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exception5:
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rti
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exception6:
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rti
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exception7:
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rti
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