mirror of
https://github.com/libretro/dolphin
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636 lines
22 KiB
C++
636 lines
22 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: disasm.h 12420 2014-07-18 11:14:25Z sshwarts $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2014 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef _BX_DISASM_H_
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#define _BX_DISASM_H_
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#include "config.h"
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#define BX_DECODE_MODRM(modrm_byte, mod, opcode, rm) { \
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mod = (modrm_byte >> 6) & 0x03; \
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opcode = (modrm_byte >> 3) & 0x07; \
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rm = modrm_byte & 0x07; \
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}
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#define BX_DECODE_SIB(sib_byte, scale, index, base) { \
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scale = sib_byte >> 6; \
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index = (sib_byte >> 3) & 0x07; \
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base = sib_byte & 0x07; \
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}
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/* Instruction set attributes (duplicated in cpu.h) */
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#define IA_X87 (BX_CONST64(1) << 0) /* FPU (X87) instruction */
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#define IA_486 (BX_CONST64(1) << 1) /* 486 new instruction */
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#define IA_PENTIUM (BX_CONST64(1) << 2) /* Pentium new instruction */
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#define IA_P6 (BX_CONST64(1) << 3) /* P6 new instruction */
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#define IA_MMX (BX_CONST64(1) << 4) /* MMX instruction */
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#define IA_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction (AMD) */
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#define IA_SYSCALL_SYSRET (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode (AMD) */
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#define IA_SYSENTER_SYSEXIT (BX_CONST64(1) << 7) /* SYSENTER/SYSEXIT instruction */
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#define IA_CLFLUSH (BX_CONST64(1) << 8) /* CLFLUSH instruction */
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#define IA_SSE (BX_CONST64(1) << 9) /* SSE instruction */
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#define IA_SSE2 (BX_CONST64(1) << 10) /* SSE2 instruction */
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#define IA_SSE3 (BX_CONST64(1) << 11) /* SSE3 instruction */
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#define IA_SSSE3 (BX_CONST64(1) << 12) /* SSSE3 instruction */
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#define IA_SSE4_1 (BX_CONST64(1) << 13) /* SSE4_1 instruction */
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#define IA_SSE4_2 (BX_CONST64(1) << 14) /* SSE4_2 instruction */
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#define IA_POPCNT (BX_CONST64(1) << 15) /* POPCNT instruction */
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#define IA_MONITOR_MWAIT (BX_CONST64(1) << 16) /* MONITOR/MWAIT instruction */
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#define IA_VMX (BX_CONST64(1) << 17) /* VMX instruction */
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#define IA_SMX (BX_CONST64(1) << 18) /* SMX instruction */
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#define IA_LM_LAHF_SAHF (BX_CONST64(1) << 19) /* Long Mode LAHF/SAHF instruction */
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#define IA_CMPXCHG16B (BX_CONST64(1) << 20) /* CMPXCHG16B instruction */
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#define IA_RDTSCP (BX_CONST64(1) << 21) /* RDTSCP instruction */
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#define IA_XSAVE (BX_CONST64(1) << 22) /* XSAVE/XRSTOR extensions instruction */
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#define IA_XSAVEOPT (BX_CONST64(1) << 23) /* XSAVEOPT instruction */
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#define IA_AES_PCLMULQDQ (BX_CONST64(1) << 24) /* AES+PCLMULQDQ instruction */
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#define IA_MOVBE (BX_CONST64(1) << 25) /* MOVBE Intel Atom(R) instruction */
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#define IA_FSGSBASE (BX_CONST64(1) << 26) /* FS/GS BASE access instruction */
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#define IA_INVPCID (BX_CONST64(1) << 27) /* INVPCID instruction */
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#define IA_AVX (BX_CONST64(1) << 28) /* AVX instruction */
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#define IA_AVX2 (BX_CONST64(1) << 29) /* AVX2 instruction */
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#define IA_AVX_F16C (BX_CONST64(1) << 30) /* AVX F16 convert instruction */
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#define IA_AVX_FMA (BX_CONST64(1) << 31) /* AVX FMA instruction */
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#define IA_SSE4A (BX_CONST64(1) << 32) /* SSE4A instruction (AMD) */
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#define IA_LZCNT (BX_CONST64(1) << 33) /* LZCNT instruction */
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#define IA_BMI1 (BX_CONST64(1) << 34) /* BMI1 instruction */
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#define IA_BMI2 (BX_CONST64(1) << 35) /* BMI2 instruction */
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#define IA_FMA4 (BX_CONST64(1) << 36) /* FMA4 instruction (AMD) */
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#define IA_XOP (BX_CONST64(1) << 37) /* XOP instruction (AMD) */
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#define IA_TBM (BX_CONST64(1) << 38) /* TBM instruction (AMD) */
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#define IA_SVM (BX_CONST64(1) << 39) /* SVM instruction (AMD) */
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#define IA_RDRAND (BX_CONST64(1) << 40) /* RDRAND instruction */
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#define IA_ADX (BX_CONST64(1) << 41) /* ADCX/ADOX instruction */
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#define IA_SMAP (BX_CONST64(1) << 42) /* SMAP support */
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#define IA_RDSEED (BX_CONST64(1) << 43) /* RDSEED instruction */
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#define IA_SHA (BX_CONST64(1) << 44) /* SHA instruction */
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#define IA_AVX512 (BX_CONST64(1) << 45) /* AVX-512 instruction */
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#define IA_AVX512_CD (BX_CONST64(1) << 46) /* AVX-512 Conflict Detection instruction */
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#define IA_AVX512_PF (BX_CONST64(1) << 47) /* AVX-512 Sparse Prefetch instruction */
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#define IA_AVX512_ER (BX_CONST64(1) << 48) /* AVX-512 Exponential/Reciprocal instruction */
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#define IA_AVX512_DQ (BX_CONST64(1) << 49) /* AVX-512DQ instruction */
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#define IA_AVX512_BW (BX_CONST64(1) << 50) /* AVX-512 Byte/Word instruction */
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#define IA_CLFLUSHOPT (BX_CONST64(1) << 51) /* CLFLUSHOPT instruction */
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#define IA_XSAVEC (BX_CONST64(1) << 52) /* XSAVEC instruction */
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#define IA_XSAVES (BX_CONST64(1) << 53) /* XSAVES instruction */
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/* general purpose bit register */
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enum {
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rAX_REG,
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rCX_REG,
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rDX_REG,
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rBX_REG,
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rSP_REG,
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rBP_REG,
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rSI_REG,
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rDI_REG
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};
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/* segment register */
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enum {
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ES_REG,
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CS_REG,
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SS_REG,
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DS_REG,
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FS_REG,
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GS_REG,
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INVALID_SEG1,
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INVALID_SEG2
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};
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class disassembler;
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struct x86_insn;
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typedef void (disassembler::*BxDisasmPtr_t)(const x86_insn *insn);
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typedef void (disassembler::*BxDisasmResolveModrmPtr_t)(const x86_insn *insn, unsigned attr);
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struct BxDisasmOpcodeInfo_t
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{
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const char *IntelOpcode;
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const char *AttOpcode;
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BxDisasmPtr_t Operand1;
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BxDisasmPtr_t Operand2;
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BxDisasmPtr_t Operand3;
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BxDisasmPtr_t Operand4;
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Bit64u Feature;
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};
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struct BxDisasmOpcodeTable_t
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{
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Bit32u Attr;
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const void *OpcodeInfo;
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};
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// segment override not used
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#define NO_SEG_OVERRIDE 0xFF
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// datasize attributes
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#define X_SIZE 0x00 /* no size */
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#define B_SIZE 0x01 /* byte */
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#define W_SIZE 0x02 /* word */
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#define D_SIZE 0x03 /* double word */
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#define Q_SIZE 0x04 /* quad word */
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#define Z_SIZE 0x05 /* double word in 32-bit mode, quad word in 64-bit mode */
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#define T_SIZE 0x06 /* 10-byte x87 floating point */
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#define XMM_SIZE 0x07 /* double quad word (XMM) */
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#define YMM_SIZE 0x08 /* quadruple quad word (YMM) */
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#define VSIB_Index 0x80
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// branch hint attribute
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#define BRANCH_HINT 0x1000
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struct x86_insn
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{
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public:
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x86_insn(bx_bool is32, bx_bool is64);
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bx_bool is_seg_override() const {
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return (seg_override != NO_SEG_OVERRIDE);
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}
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public:
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bx_bool is_32, is_64;
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bx_bool as_32, as_64;
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bx_bool os_32, os_64;
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Bit8u extend8b;
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Bit8u rex_r, rex_x, rex_b;
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Bit8u seg_override;
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unsigned b1;
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unsigned ilen;
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#define BX_AVX_VL128 0
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#define BX_AVX_VL256 1
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Bit8u vex_vvv, vex_l, vex_w;
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int is_vex; // 0 - no VEX used, 1 - VEX is used, -1 - invalid VEX
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int is_evex; // 0 - no EVEX used, 1 - EVEX is used, -1 - invalid EVEX
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int is_xop; // 0 - no XOP used, 1 - XOP is used, -1 - invalid XOP
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Bit8u modrm, mod, nnn, rm;
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Bit8u sib, scale, index, base;
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union {
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Bit16u displ16;
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Bit32u displ32;
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} displacement;
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bx_bool evex_b;
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bx_bool evex_z;
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unsigned evex_ll_rc;
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};
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BX_CPP_INLINE x86_insn::x86_insn(bx_bool is32, bx_bool is64)
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{
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is_32 = is32;
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is_64 = is64;
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if (is_64) {
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os_64 = 0;
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as_64 = 1;
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os_32 = 1;
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as_32 = 1;
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}
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else {
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os_64 = 0;
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as_64 = 0;
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os_32 = is_32;
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as_32 = is_32;
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}
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extend8b = 0;
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rex_r = rex_b = rex_x = 0;
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seg_override = NO_SEG_OVERRIDE;
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ilen = 0;
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b1 = 0;
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is_vex = 0;
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is_evex = 0;
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is_xop = 0;
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vex_vvv = 0;
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vex_l = BX_AVX_VL128;
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vex_w = 0;
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modrm = mod = nnn = rm = 0;
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sib = scale = index = base = 0;
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displacement.displ32 = 0;
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evex_b = 0;
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evex_ll_rc = 0;
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evex_z = 0;
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}
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class disassembler {
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public:
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disassembler(): offset_mode_hex(0), print_mem_datasize(1) { set_syntax_intel(); }
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unsigned disasm(bx_bool is_32, bx_bool is_64, bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf);
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unsigned disasm16(bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return disasm(0, 0, cs_base, ip, instr, disbuf); }
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unsigned disasm32(bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return disasm(1, 0, cs_base, ip, instr, disbuf); }
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unsigned disasm64(bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return disasm(1, 1, cs_base, ip, instr, disbuf); }
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x86_insn decode(bx_bool is_32, bx_bool is_64, bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf);
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x86_insn decode16(bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return decode(0, 0, cs_base, ip, instr, disbuf); }
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x86_insn decode32(bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return decode(1, 0, cs_base, ip, instr, disbuf); }
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x86_insn decode64(bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return decode(1, 1, cs_base, ip, instr, disbuf); }
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void set_syntax_intel();
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void set_syntax_att();
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void set_offset_mode_hex(bx_bool mode) { offset_mode_hex = mode; }
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void set_mem_datasize_print(bx_bool mode) { print_mem_datasize = mode; }
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void toggle_syntax_mode();
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private:
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bx_bool intel_mode, offset_mode_hex, print_mem_datasize;
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const char **general_16bit_regname;
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const char **general_8bit_regname;
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const char **general_32bit_regname;
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const char **general_8bit_regname_rex;
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const char **general_64bit_regname;
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const char **segment_name;
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const char **index16;
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const char **vector_reg_name;
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const char *sreg_mod00_base32[16];
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const char *sreg_mod01or10_base32[16];
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const char *sreg_mod00_rm16[8];
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const char *sreg_mod01or10_rm16[8];
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private:
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bx_address db_eip, db_cs_base;
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const Bit8u *instruction; // for fetching of next byte of instruction
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char *disbufptr;
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BxDisasmResolveModrmPtr_t resolve_modrm;
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BX_CPP_INLINE Bit8u fetch_byte() {
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db_eip++;
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return(*instruction++);
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};
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BX_CPP_INLINE Bit8u peek_byte() {
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return(*instruction);
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};
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BX_CPP_INLINE Bit16u fetch_word() {
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Bit8u b0 = * (Bit8u *) instruction++;
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Bit8u b1 = * (Bit8u *) instruction++;
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Bit16u ret16 = (b1<<8) | b0;
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db_eip += 2;
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return(ret16);
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};
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BX_CPP_INLINE Bit32u fetch_dword() {
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Bit8u b0 = * (Bit8u *) instruction++;
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Bit8u b1 = * (Bit8u *) instruction++;
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Bit8u b2 = * (Bit8u *) instruction++;
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Bit8u b3 = * (Bit8u *) instruction++;
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Bit32u ret32 = (b3<<24) | (b2<<16) | (b1<<8) | b0;
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db_eip += 4;
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return(ret32);
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};
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BX_CPP_INLINE Bit64u fetch_qword() {
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Bit64u d0 = fetch_dword();
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Bit64u d1 = fetch_dword();
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Bit64u ret64 = (d1<<32) | d0;
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return(ret64);
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};
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void dis_putc(char symbol);
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void dis_sprintf(const char *fmt, ...);
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void decode_modrm(x86_insn *insn);
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unsigned decode_vex(x86_insn *insn);
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unsigned decode_evex(x86_insn *insn);
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unsigned decode_xop(x86_insn *insn);
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void resolve16_mod0 (const x86_insn *insn, unsigned mode);
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void resolve16_mod1or2(const x86_insn *insn, unsigned mode);
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void resolve32_mod0 (const x86_insn *insn, unsigned mode);
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void resolve32_mod1or2(const x86_insn *insn, unsigned mode);
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void resolve32_mod0_rm4 (const x86_insn *insn, unsigned mode);
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void resolve32_mod1or2_rm4(const x86_insn *insn, unsigned mode);
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void resolve64_mod0 (const x86_insn *insn, unsigned mode);
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void resolve64_mod1or2(const x86_insn *insn, unsigned mode);
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void resolve64_mod0_rm4 (const x86_insn *insn, unsigned mode);
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void resolve64_mod1or2_rm4(const x86_insn *insn, unsigned mode);
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void initialize_modrm_segregs();
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void print_datasize(unsigned mode);
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void print_memory_access16(int datasize,
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const char *seg, const char *index, Bit16u disp);
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void print_memory_access32(int datasize,
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const char *seg, const char *base, const char *index, int scale, Bit32s disp);
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void print_memory_access64(int datasize,
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const char *seg, const char *base, const char *index, int scale, Bit32s disp);
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void print_disassembly_intel(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry);
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void print_disassembly_att (const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry);
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public:
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/*
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* Codes for Addressing Method:
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* ---------------------------
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* A - Direct address. The instruction has no ModR/M byte; the address
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* of the operand is encoded in the instruction; and no base register,
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* index register, or scaling factor can be applied.
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* C - The reg field of the ModR/M byte selects a control register.
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* D - The reg field of the ModR/M byte selects a debug register.
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* E - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either a general-purpose register or a memory address.
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* In case of the register operand, the R/M field of the ModR/M byte
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* selects a general register.
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* F - Flags Register.
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* G - The reg field of the ModR/M byte selects a general register.
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* I - Immediate data. The operand value is encoded in subsequent bytes of
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* the instruction.
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* J - The instruction contains a relative offset to be added to the
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* instruction pointer register.
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* M - The ModR/M byte may refer only to memory.
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* N - The R/M field of the ModR/M byte selects a packed-quadword MMX
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technology register.
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* O - The instruction has no ModR/M byte; the offset of the operand is
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* coded as a word or double word (depending on address size attribute)
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* in the instruction. No base register, index register, or scaling
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* factor can be applied.
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* P - The reg field of the ModR/M byte selects a packed quadword MMX
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* technology register.
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* Q - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either an MMX technology register or a memory address.
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* If it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
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* index register, a scaling factor, and a displacement.
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* R - The mod field of the ModR/M byte may refer only to a general register.
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* S - The reg field of the ModR/M byte selects a segment register.
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* T - The reg field of the ModR/M byte selects a test register.
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* U - The R/M field of the ModR/M byte selects a 128-bit XMM/256-bit YMM register.
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* V - The reg field of the ModR/M byte selects a 128-bit XMM/256-bit YMM register.
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* W - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either a 128-bit XMM/256-bit YMM register or a memory address.
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* If it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
|
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* index register, a scaling factor, and a displacement.
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* X - Memory addressed by the DS:rSI register pair.
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* Y - Memory addressed by the ES:rDI register pair.
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*/
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|
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/*
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* Codes for Operand Type:
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* ----------------------
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* a - Two one-word operands in memory or two double-word operands in
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* memory, depending on operand-size attribute (used only by the BOUND
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|
* instruction).
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* b - Byte, regardless of operand-size attribute.
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* d - Doubleword, regardless of operand-size attribute.
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* dq - Double-quadword, regardless of operand-size attribute.
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* p - 32-bit or 48-bit pointer, depending on operand-size attribute.
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* pd - 128-bit/256-bit packed double-precision floating-point data.
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|
* pi - Quadword MMX technology register (packed integer)
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|
* ps - 128-bit/256-bit packed single-precision floating-point data.
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|
* q - Quadword, regardless of operand-size attribute.
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* s - 6-byte or 10-byte pseudo-descriptor.
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* si - Doubleword integer register (scalar integer)
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|
* ss - Scalar element of a packed single-precision floating data.
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* sd - Scalar element of a packed double-precision floating data.
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|
* v - Word, doubleword or quadword, depending on operand-size attribute.
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|
* w - Word, regardless of operand-size attr.
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|
* y - Doubleword or quadword (in 64-bit mode) depending on 32/64 bit
|
|
* operand size.
|
|
*/
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|
|
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// far call/jmp
|
|
void Apw(const x86_insn *insn);
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|
void Apd(const x86_insn *insn);
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|
|
|
// 8-bit general purpose registers
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|
void AL_Reg(const x86_insn *insn);
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|
void CL_Reg(const x86_insn *insn);
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|
|
|
// 16-bit general purpose registers
|
|
void AX_Reg(const x86_insn *insn);
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|
void DX_Reg(const x86_insn *insn);
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|
|
|
// 32-bit general purpose registers
|
|
void EAX_Reg(const x86_insn *insn);
|
|
|
|
// 64-bit general purpose registers
|
|
void RAX_Reg(const x86_insn *insn);
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|
void RCX_Reg(const x86_insn *insn);
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|
|
|
// segment registers
|
|
void CS(const x86_insn *insn);
|
|
void DS(const x86_insn *insn);
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|
void ES(const x86_insn *insn);
|
|
void SS(const x86_insn *insn);
|
|
void FS(const x86_insn *insn);
|
|
void GS(const x86_insn *insn);
|
|
|
|
// segment registers
|
|
void Sw(const x86_insn *insn);
|
|
|
|
// control register
|
|
void Cd(const x86_insn *insn);
|
|
void Cq(const x86_insn *insn);
|
|
|
|
// debug register
|
|
void Dd(const x86_insn *insn);
|
|
void Dq(const x86_insn *insn);
|
|
|
|
// 8-bit general purpose register
|
|
void Reg8(const x86_insn *insn);
|
|
|
|
// 16-bit general purpose register
|
|
void RX(const x86_insn *insn);
|
|
|
|
// 32-bit general purpose register
|
|
void ERX(const x86_insn *insn);
|
|
|
|
// 64-bit general purpose register
|
|
void RRX(const x86_insn *insn);
|
|
|
|
// general purpose register or memory operand
|
|
void Eb(const x86_insn *insn);
|
|
void Ew(const x86_insn *insn);
|
|
void Ed(const x86_insn *insn);
|
|
void Eq(const x86_insn *insn);
|
|
void Ey(const x86_insn *insn);
|
|
void Ebd(const x86_insn *insn);
|
|
void Ewd(const x86_insn *insn);
|
|
void Edq(const x86_insn *insn);
|
|
|
|
// general purpose register
|
|
void Gb(const x86_insn *insn);
|
|
void Gw(const x86_insn *insn);
|
|
void Gd(const x86_insn *insn);
|
|
void Gq(const x86_insn *insn);
|
|
void Gy(const x86_insn *insn);
|
|
|
|
// vex encoded general purpose register
|
|
void By(const x86_insn *insn);
|
|
|
|
// immediate
|
|
void I1(const x86_insn *insn);
|
|
void Ib(const x86_insn *insn);
|
|
void Iw(const x86_insn *insn);
|
|
void Id(const x86_insn *insn);
|
|
void Iq(const x86_insn *insn);
|
|
|
|
// double immediate
|
|
void IbIb(const x86_insn *insn);
|
|
void IwIb(const x86_insn *insn);
|
|
|
|
// sign extended immediate
|
|
void sIbw(const x86_insn *insn);
|
|
void sIbd(const x86_insn *insn);
|
|
void sIbq(const x86_insn *insn);
|
|
void sIdq(const x86_insn *insn);
|
|
|
|
// floating point
|
|
void ST0(const x86_insn *insn);
|
|
void STi(const x86_insn *insn);
|
|
|
|
// general purpose register
|
|
void Rw(const x86_insn *insn);
|
|
void Rd(const x86_insn *insn);
|
|
void Rq(const x86_insn *insn);
|
|
void Ry(const x86_insn *insn);
|
|
|
|
// mmx register
|
|
void Pq(const x86_insn *insn);
|
|
|
|
// mmx register or memory operand
|
|
void Qd(const x86_insn *insn);
|
|
void Qq(const x86_insn *insn);
|
|
void Vq(const x86_insn *insn);
|
|
void Nq(const x86_insn *insn);
|
|
|
|
// xmm/ymm register
|
|
void Ups(const x86_insn *insn);
|
|
void Upd(const x86_insn *insn);
|
|
void Udq(const x86_insn *insn);
|
|
void Uq(const x86_insn *insn);
|
|
|
|
void Vdq(const x86_insn *insn);
|
|
void Vss(const x86_insn *insn);
|
|
void Vsd(const x86_insn *insn);
|
|
void Vps(const x86_insn *insn);
|
|
void Vpd(const x86_insn *insn);
|
|
// xmm/ymm register through imm byte
|
|
void VIb(const x86_insn *insn);
|
|
|
|
// xmm/ymm register or memory operand
|
|
void Wb(const x86_insn *insn);
|
|
void Ww(const x86_insn *insn);
|
|
void Wd(const x86_insn *insn);
|
|
void Wq(const x86_insn *insn);
|
|
|
|
void Wdq(const x86_insn *insn);
|
|
void Wss(const x86_insn *insn);
|
|
void Wsd(const x86_insn *insn);
|
|
void Wps(const x86_insn *insn);
|
|
void Wpd(const x86_insn *insn);
|
|
|
|
// vex encoded xmm/ymm register
|
|
void Hdq(const x86_insn *insn);
|
|
void Hps(const x86_insn *insn);
|
|
void Hpd(const x86_insn *insn);
|
|
void Hss(const x86_insn *insn);
|
|
void Hsd(const x86_insn *insn);
|
|
|
|
// direct memory access
|
|
void OP_O(const x86_insn *insn, unsigned size);
|
|
void Ob(const x86_insn *insn);
|
|
void Ow(const x86_insn *insn);
|
|
void Od(const x86_insn *insn);
|
|
void Oq(const x86_insn *insn);
|
|
|
|
// memory operand
|
|
void OP_M(const x86_insn *insn, unsigned size);
|
|
void Ma(const x86_insn *insn);
|
|
void Mp(const x86_insn *insn);
|
|
void Ms(const x86_insn *insn);
|
|
void Mx(const x86_insn *insn);
|
|
void Mb(const x86_insn *insn);
|
|
void Mw(const x86_insn *insn);
|
|
void Md(const x86_insn *insn);
|
|
void Mq(const x86_insn *insn);
|
|
void Mt(const x86_insn *insn);
|
|
void Mdq(const x86_insn *insn);
|
|
void Mps(const x86_insn *insn);
|
|
void Mpd(const x86_insn *insn);
|
|
void Mss(const x86_insn *insn);
|
|
void Msd(const x86_insn *insn);
|
|
|
|
// gather VSib
|
|
void VSib(const x86_insn *insn);
|
|
|
|
// string instructions
|
|
void OP_X(const x86_insn *insn, unsigned size);
|
|
void Xb(const x86_insn *insn);
|
|
void Xw(const x86_insn *insn);
|
|
void Xd(const x86_insn *insn);
|
|
void Xq(const x86_insn *insn);
|
|
|
|
// string instructions
|
|
void OP_Y(const x86_insn *insn, unsigned size);
|
|
void Yb(const x86_insn *insn);
|
|
void Yw(const x86_insn *insn);
|
|
void Yd(const x86_insn *insn);
|
|
void Yq(const x86_insn *insn);
|
|
|
|
// maskmovdq/maskmovdqu
|
|
void OP_sY(const x86_insn *insn, unsigned size);
|
|
void sYq(const x86_insn *insn);
|
|
void sYdq(const x86_insn *insn);
|
|
|
|
// jump offset
|
|
void Jb(const x86_insn *insn);
|
|
void Jw(const x86_insn *insn);
|
|
void Jd(const x86_insn *insn);
|
|
};
|
|
|
|
#endif
|